1. Field
The present technology relates to integrated circuit technology including new methods of operating memory cells.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. As the density increases in memory devices, and the floating gate memory cells get closer and closer together, interference between the charge stored in adjacent floating gates becomes a problem. This is limiting the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping memory cell, which uses a dielectric charge trapping layer in place of the floating gate. Charge trapping memory cells use dielectric charge trapping material that does not cause cell-to-cell interference like that encountered with floating gate technology, and is expected to be applied for higher density flash memory.
One advantage of dielectric charge trapping memory cells over floating gate memory cells, is that the charge can be trapped in discrete and separate locations within the charge trapping layer for each individual memory cell. Circuit designers have used such advantage to increase the amount of data that can be stored for a number of memory cells within an array of memory cells. Specifically, by storing charge at two separate locations in the charge trapping layer of a memory cell, each memory cell can store more than one bit of data. For example, so called “mirror bit” technology has been used in which two bits of data are stored in a dielectric charge trapping memory cell at two different sites. Examples of dielectric charge trapping flash memory can be seen in patent application Publication No. US 2010/0074007; Application No. 12/234,737, entitled “Flash Mirror Bit Architecture Using Single Program and Erase Entity as Logical Cell.”
While dielectric charge trapping memory technologies have continued to develop, problems with data retention in such charge trapping memory cells can occur. For example, memory cells in a high threshold state that is established by trapping electrons, or negative charge, in the charge trapping layer, can lose charge over time. With sufficient charge loss, the data value stored in the cell can be lost. The charge retention can be a particular problem in advanced memory designs, including thin film transistor memory devices and in 3D stacked memory devices.
It is therefore desirable to provide a dielectric charge trapping memory cell array design with improved data retention rates.